
#include "define.h"
#include <string.h>


void Init(void)
{
	DINT;
	IER = 0X0000U;
	IFR = 0X0000U;  
	memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (&RamfuncsLoadEnd - &RamfuncsLoadStart));

	//init system
    InitPLL();
    InitClock();
    InitFlash();

	InitPIECtrl();
	InitPieVectTable();

	//init peripheral
//    InitSciGpio();
//    InitSCI();

    InitXintf16Gpio();
    InitXINTF();

    InitEPWM();
    EpwmDBConfig();
    InitEPwmGpio();

    InitECanaGpio();
    InitECan();

//	InitECAP();
	InitADC();

    //init extern chip
    InitRdcGpio();
    InitRdc();

    InitSysGpio();
	InitSoftware();

	IER = IER | BIT2 | BIT3 | BIT7 | BIT8;
	EINT;
	ERTM;

    return;
}


void InitPLL(void)
{
    EALLOW;

    SysCtrlRegs.WDCR = 0X0068U; /*禁止看门狗*/

    if(SysCtrlRegs.PLLSTS.bit.MCLKSTS  == 1U)/*Missing Clock*/
    {
        while(1)
        {
            ;
        }
    }
    /*时钟分频位大于1*/
    if(SysCtrlRegs.PLLSTS.bit.DIVSEL > 1U)
    {
        SysCtrlRegs.PLLSTS.bit.DIVSEL = 0U;
    }

    SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1U;  /*时钟丢失检测位置为1，使能检测*/
    SysCtrlRegs.PLLCR.bit.DIV = 0X8U;  /*时钟倍频位置为8*/
    //SysCtrlRegs.PLLCR.bit.DIV = 0X2U;
    //SysCtrlRegs.PLLCR.bit.DIV = 0X4U;
    /*锁定状态位为0*/
    while(SysCtrlRegs.PLLSTS.bit.PLLLOCKS == 0U)
    {
        ;
    }
    SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1U; /*时钟丢失检测位置为1*/
    SysCtrlRegs.PLLSTS.bit.DIVSEL = 2U;  /*时钟分频位置为2*/

    EDIS;

    return;
}


void InitClock(void)
{
    Uint16 uiLoop = 0U;

    EALLOW;

    SysCtrlRegs.HISPCP.all = 0X0000U;   /*set high peripheral clock to 120MHZ*/
    SysCtrlRegs.LOSPCP.all = 0X0002U;   /*set low peripheral clock to 30MHZ*/

    /*延时等待*/
    for(uiLoop = 0U;  uiLoop < 5000U; uiLoop++)
    {
        ;
    }

    /*enable clock to ADC、EPWM、GPIO、XINTF、SCI*/
    SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1U;
    SysCtrlRegs.PCLKCR0.bit.I2CAENCLK = 1U;
    SysCtrlRegs.PCLKCR0.bit.SCIAENCLK = 1U;
    SysCtrlRegs.PCLKCR0.bit.SCIBENCLK = 1U;
    SysCtrlRegs.PCLKCR0.bit.SCICENCLK = 1U;
    SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1U;
    SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 1U;
    SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 1U;
    SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 1U;
    SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 1U;
    SysCtrlRegs.PCLKCR1.bit.ECAP4ENCLK = 1U;
    SysCtrlRegs.PCLKCR3.bit.GPIOINENCLK = 1U;
    SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1U;
    SysCtrlRegs.PCLKCR0.bit.ECANAENCLK = 1U;

    EDIS;

    return;
}


#pragma CODE_SECTION(InitFlash,"ramfuncs");
void InitFlash(void)
{
    EALLOW;

    /*Enable Flash Pipeline mode*/
    FlashRegs.FOPT.bit.ENPIPE = 1U;
    /*Set the Paged Waitstate for the Flash*/
    FlashRegs.FBANKWAIT.bit.PAGEWAIT = 5U;
    /*Set the Random Waitstate for the Flash*/
    FlashRegs.FBANKWAIT.bit.RANDWAIT = 5U;
    /*Set the Waitstate for the OTP*/
    FlashRegs.FOTPWAIT.bit.OTPWAIT = 8U;
    /*THESE 2 REGISTERS SHOULD USE DEFAULT VALUE*/
    FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0X01FFU;
    FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0X01FFU;

    EDIS;
    ENFORCE_FLASH;

    return;
}


const struct PIE_VECT_TABLE PieVectTableInit =
{
    PIE_RESERVED,  // 0  Reserved space
    PIE_RESERVED,  // 1  Reserved space
    PIE_RESERVED,  // 2  Reserved space
    PIE_RESERVED,  // 3  Reserved space
    PIE_RESERVED,  // 4  Reserved space
    PIE_RESERVED,  // 5  Reserved space
    PIE_RESERVED,  // 6  Reserved space
    PIE_RESERVED,  // 7  Reserved space
    PIE_RESERVED,  // 8  Reserved space
    PIE_RESERVED,  // 9  Reserved space
    PIE_RESERVED,  // 10 Reserved space
    PIE_RESERVED,  // 11 Reserved space
    PIE_RESERVED,  // 12 Reserved space

    //
    // Non-Peripheral Interrupts
    //
    INT13_ISR,     // XINT13 or CPU-Timer 1
    INT14_ISR,     // CPU-Timer2
    DATALOG_ISR,   // Datalogging interrupt
    RTOSINT_ISR,   // RTOS interrupt
    EMUINT_ISR,    // Emulation interrupt
    NMI_ISR,       // Non-maskable interrupt
    ILLEGAL_ISR,   // Illegal operation TRAP
    USER1_ISR,     // User Defined trap 1
    USER2_ISR,     // User Defined trap 2
    USER3_ISR,     // User Defined trap 3
    USER4_ISR,     // User Defined trap 4
    USER5_ISR,     // User Defined trap 5
    USER6_ISR,     // User Defined trap 6
    USER7_ISR,     // User Defined trap 7
    USER8_ISR,     // User Defined trap 8
    USER9_ISR,     // User Defined trap 9
    USER10_ISR,    // User Defined trap 10
    USER11_ISR,    // User Defined trap 11
    USER12_ISR,    // User Defined trap 12

    //
    // Group 1 PIE Vectors
    //
    SEQ1INT_ISR,     // 1.1 ADC
    SEQ2INT_ISR,     // 1.2 ADC
    rsvd_ISR,        // 1.3
    XINT1_ISR,       // 1.4
    XINT2_ISR,       // 1.5
    ADCINT_ISR,      // 1.6 ADC
    TINT0_ISR,       // 1.7 Timer 0
    WAKEINT_ISR,     // 1.8 WD, Low Power

    //
    // Group 2 PIE Vectors
    //
    EPWM1_TZINT_ISR, // 2.1 EPWM-1 Trip Zone
    EPWM2_TZINT_ISR, // 2.2 EPWM-2 Trip Zone
    EPWM3_TZINT_ISR, // 2.3 EPWM-3 Trip Zone
    EPWM4_TZINT_ISR, // 2.4 EPWM-4 Trip Zone
    EPWM5_TZINT_ISR, // 2.5 EPWM-5 Trip Zone
    EPWM6_TZINT_ISR, // 2.6 EPWM-6 Trip Zone
    rsvd_ISR,        // 2.7
    rsvd_ISR,        // 2.8

    //
    // Group 3 PIE Vectors
    //
    EPWM1_INT_ISR,   // 3.1 EPWM-1 Interrupt
    EPWM2_INT_ISR,   // 3.2 EPWM-2 Interrupt
    EPWM3_INT_ISR,   // 3.3 EPWM-3 Interrupt
    EPWM4_INT_ISR,   // 3.4 EPWM-4 Interrupt
    EPWM5_INT_ISR,   // 3.5 EPWM-5 Interrupt
    EPWM6_INT_ISR,   // 3.6 EPWM-6 Interrupt
    rsvd_ISR,        // 3.7
    rsvd_ISR,        // 3.8

    //
    // Group 4 PIE Vectors
    //
    ECAP1_INT_ISR,   // 4.1 ECAP-1
    ECAP2_INT_ISR,   // 4.2 ECAP-2
    ECAP3_INT_ISR,   // 4.3 ECAP-3
    ECAP4_INT_ISR,   // 4.4 ECAP-4
    ECAP5_INT_ISR,   // 4.5 ECAP-5
    ECAP6_INT_ISR,   // 4.6 ECAP-6
    rsvd_ISR,        // 4.7
    rsvd_ISR,        // 4.8

    //
    // Group 5 PIE Vectors
    //
    EQEP1_INT_ISR,   // 5.1 EQEP-1
    EQEP2_INT_ISR,   // 5.2 EQEP-2
    rsvd_ISR,        // 5.3
    rsvd_ISR,        // 5.4
    rsvd_ISR,        // 5.5
    rsvd_ISR,        // 5.6
    rsvd_ISR,        // 5.7
    rsvd_ISR,        // 5.8

    //
    // Group 6 PIE Vectors
    //
    SPIRXINTA_ISR,   // 6.1 SPI-A
    SPITXINTA_ISR,   // 6.2 SPI-A
    MRINTA_ISR,      // 6.3 McBSP-A
    MXINTA_ISR,      // 6.4 McBSP-A
    MRINTB_ISR,      // 6.5 McBSP-B
    MXINTB_ISR,      // 6.6 McBSP-B
    rsvd_ISR,        // 6.7
    rsvd_ISR,        // 6.8

    //
    // Group 7 PIE Vectors
    //
    DINTCH1_ISR,     // 7.1  DMA channel 1
    DINTCH2_ISR,     // 7.2  DMA channel 2
    DINTCH3_ISR,     // 7.3  DMA channel 3
    DINTCH4_ISR,     // 7.4  DMA channel 4
    DINTCH5_ISR,     // 7.5  DMA channel 5
    DINTCH6_ISR,     // 7.6  DMA channel 6
    rsvd_ISR,        // 7.7
    rsvd_ISR,        // 7.8

    //
    // Group 8 PIE Vectors
    //
    I2CINT1A_ISR,    // 8.1  I2C
    I2CINT2A_ISR,    // 8.2  I2C
    rsvd_ISR,        // 8.3
    rsvd_ISR,        // 8.4
    SCIRXINTC_ISR,   // 8.5  SCI-C
    SCITXINTC_ISR,   // 8.6  SCI-C
    rsvd_ISR,        // 8.7
    rsvd_ISR,        // 8.8

    //
    // Group 9 PIE Vectors
    //
    SCIRXINTA_ISR,   // 9.1 SCI-A
    SCITXINTA_ISR,   // 9.2 SCI-A
    SCIRXINTB_ISR,   // 9.3 SCI-B
    SCITXINTB_ISR,   // 9.4 SCI-B
    ECAN0INTA_ISR,   // 9.5 eCAN-A
    ECAN1INTA_ISR,   // 9.6 eCAN-A
    ECAN0INTB_ISR,   // 9.7 eCAN-B
    ECAN1INTB_ISR,   // 9.8 eCAN-B

    //
    // Group 10 PIE Vectors
    //
    rsvd_ISR,        // 10.1
    rsvd_ISR,        // 10.2
    rsvd_ISR,        // 10.3
    rsvd_ISR,        // 10.4
    rsvd_ISR,        // 10.5
    rsvd_ISR,        // 10.6
    rsvd_ISR,        // 10.7
    rsvd_ISR,        // 10.8

    //
    // Group 11 PIE Vectors
    //
    rsvd_ISR,        // 11.1
    rsvd_ISR,        // 11.2
    rsvd_ISR,        // 11.3
    rsvd_ISR,        // 11.4
    rsvd_ISR,        // 11.5
    rsvd_ISR,        // 11.6
    rsvd_ISR,        // 11.7
    rsvd_ISR,        // 11.8

    //
    // Group 12 PIE Vectors
    //
    XINT3_ISR,       // 12.1
    XINT4_ISR,       // 12.2
    XINT5_ISR,       // 12.3
    XINT6_ISR,       // 12.4
    XINT7_ISR,       // 12.5
    rsvd_ISR,        // 12.6
    LVF_ISR,         // 12.7
    LUF_ISR,         // 12.8
};
void InitPieVectTable(void)
{
    Uint16 uiLoop = 0U;
    Uint32 *p_ulSource = (void *) &PieVectTableInit;
    Uint32 *p_ulDest = (void *) &PieVectTable;

    EALLOW;

    for(uiLoop = 0U; uiLoop < 128U; uiLoop++)
    {
        (*p_ulDest) = (*p_ulSource);
        p_ulSource++;
        p_ulDest++;
    }
    EDIS;

    return;
}

void InitPIECtrl(void)
{
    DINT;

    //Disable the PIE
    PieCtrlRegs.PIECTRL.bit.ENPIE = 0;

    // Clear all PIEIER registers
    PieCtrlRegs.PIEIER1.all = 0U;
    PieCtrlRegs.PIEIER2.all = 0U;
    PieCtrlRegs.PIEIER3.all = 0U;
    PieCtrlRegs.PIEIER4.all = 0U;
    PieCtrlRegs.PIEIER5.all = 0U;
    PieCtrlRegs.PIEIER6.all = 0U;
    PieCtrlRegs.PIEIER7.all = 0U;
    PieCtrlRegs.PIEIER8.all = 0U;
    PieCtrlRegs.PIEIER9.all = 0U;
    PieCtrlRegs.PIEIER10.all = 0U;
    PieCtrlRegs.PIEIER11.all = 0U;
    PieCtrlRegs.PIEIER12.all = 0U;

    // Clear all PIEIFR registers
    PieCtrlRegs.PIEIFR1.all = 0U;
    PieCtrlRegs.PIEIFR2.all = 0U;
    PieCtrlRegs.PIEIFR3.all = 0U;
    PieCtrlRegs.PIEIFR4.all = 0U;
    PieCtrlRegs.PIEIFR5.all = 0U;
    PieCtrlRegs.PIEIFR6.all = 0U;
    PieCtrlRegs.PIEIFR7.all = 0U;
    PieCtrlRegs.PIEIFR8.all = 0U;
    PieCtrlRegs.PIEIFR9.all = 0U;
    PieCtrlRegs.PIEIFR10.all = 0U;
    PieCtrlRegs.PIEIFR11.all = 0U;
    PieCtrlRegs.PIEIFR12.all = 0U;

    // Enable the PIEIER
    PieCtrlRegs.PIEIER3.bit.INTx1 = 1;//ePWM1

    // Enables PIE to drive a pulse into the CPU
    PieCtrlRegs.PIEACK.all = 0XFFFFU;

    // Enable the PIE
    PieCtrlRegs.PIECTRL.bit.ENPIE = 1;

    EINT;

    return;
}

void InitSciGpio(void)
{
    EALLOW;

    //SCI-A
    GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0;  // Enable pull-up for GPIO28 (SCIRXDA)
    GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0;	 // Enable pull-up for GPIO29 (SCITXDA)

    GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3;  // Asynch input GPIO28 (SCIRXDA)

    GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1;   // Configure GPIO28 to SCIRXDA
    GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1;   // Configure GPIO29 to SCITXDA

    EDIS;
}
void InitSCI(void)
{
	SciaRegs.SCICTL1.bit.SWRESET = 0U;/*SCI-B复位*/
	SciaRegs.SCICCR.bit.PARITYENA = 1U;/*使能奇偶校验*/
	SciaRegs.SCICCR.bit.PARITY = 0U;/*奇校验*/
	SciaRegs.SCICCR.bit.SCICHAR = 7U;/*字长8位*/
	SciaRegs.SCICCR.bit.STOPBITS = 0U;/*1位停止位*/
	/*SCIA发送器和接收器使能 */
	SciaRegs.SCICTL1.bit.RXENA = 1U;/*使能接收*/
	SciaRegs.SCICTL1.bit.TXENA = 1U;/*使能发送*/
	SciaRegs.SCICTL2.bit.TXINTENA = 0U;/*禁止发送中断*/
	/*波特率为115200bps*/
	SciaRegs.SCIHBAUD = 0X0000U;
	SciaRegs.SCILBAUD = 0X001FU;
	SciaRegs.SCIFFTX.bit.SCIFFENA = 1; /*使能FIFO功能*/
	SciaRegs.SCIFFTX.bit.TXFFIENA = 0U; /*禁止发送FIFO中断*/
	SciaRegs.SCIFFTX.bit.SCIRST = 1U; /*复位FIFO*/
	SciaRegs.SCIFFRX.bit.RXFIFORESET = 1U; /*复位rxFIFO*/
	SciaRegs.SCICTL1.bit.SWRESET = 1U;/*SCI-B复位   */
}

void InitXINTF(void)
{
	//Uint32 ulTestData = 0UL;

    EALLOW;

    //XintfRegs.XTIMING6.bit.XSIZE = 0U;  /*set Zone6 to 32 bits*/
    XintfRegs.XTIMING6.bit.XSIZE = 3U;   /*set Zone6 to 16 bits*/
    XintfRegs.XTIMING6.bit.USEREADY = 0U; /*The XREADY signal is ignored when accesses are made to the zone.*/
    XintfRegs.XTIMING6.bit.X2TIMING = 1U;

    XintfRegs.XTIMING7.bit.X2TIMING = 1U;
    XintfRegs.XTIMING7.bit.XSIZE = 3U;   /*set Zone6 to 16 bits*/
    XintfRegs.XTIMING7.bit.USEREADY = 0U; /*The XREADY signal is ignored when accesses are made to the zone.*/

    XintfRegs.XINTCNF2.bit.CLKOFF = 1U; /*Disable XCLKOUT*/
    XintfRegs.XINTCNF2.bit.WRBUFF = 3U;
    XintfRegs.XINTCNF2.bit.XTIMCLK = 1U;


    ENFORCE_FLASH;

	SysCtrlRegs.WDCR = 0X0028U;

   /* *(Uint32 *)0X1000F0UL = 0X5555AAAAUL;
    ulTestData = *(Uint32 *)0X1000F0UL;*/

	SysCtrlRegs.WDCR = 0X0068U;

    EDIS;

    return;
}


void InitXintf16Gpio(void)
{
    EALLOW;
    //mux
    GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 3;  // XD15
    GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 3;  // XD14
    GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 3;  // XD13
    GpioCtrlRegs.GPCMUX1.bit.GPIO67 = 3;  // XD12
    GpioCtrlRegs.GPCMUX1.bit.GPIO68 = 3;  // XD11
    GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 3;  // XD10
    GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 3;  // XD19
    GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 3;  // XD8
    GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3;  // XD7
    GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3;  // XD6
    GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3;  // XD5
    GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3;  // XD4
    GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3;  // XD3
    GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3;  // XD2
    GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3;  // XD1
    GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3;  // XD0

    GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3;  // XA0/XWE1n
    GpioCtrlRegs.GPBMUX1.bit.GPIO41 = 3;  // XA1
    GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3;  // XA2
    GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3;  // XA3
    GpioCtrlRegs.GPBMUX1.bit.GPIO44 = 3;  // XA4
    GpioCtrlRegs.GPBMUX1.bit.GPIO45 = 3;  // XA5
    GpioCtrlRegs.GPBMUX1.bit.GPIO46 = 3;  // XA6
    GpioCtrlRegs.GPBMUX1.bit.GPIO47 = 3;  // XA7

    GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 3;  // XA8
    GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 3;  // XA9
    GpioCtrlRegs.GPCMUX2.bit.GPIO82 = 3;  // XA10
    GpioCtrlRegs.GPCMUX2.bit.GPIO83 = 3;  // XA11
    GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 3;  // XA12
    GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 3;  // XA13
    GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 3;  // XA14
    GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 3;  // XA15
    GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 3;  // XA16
    //GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 3;  // XA17
    //GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 3;  // XA18
    //GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3;  // XA19

    //GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3;  // XREADY
    //GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3;  // XRNW
    GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3;  // XWE0

    GpioCtrlRegs.GPBMUX1.bit.GPIO36 = 3;  // XZCS0
    GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3;  // XZCS7   AD2S80
    //GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3;  // XZCS6
    EDIS;
    return;
}




void InitEPWM(void)
{
	/*
		閿熸枻鎷烽敓鍙鎷烽敓鏂ゆ嫹閿熸枻鎷蜂负50us閿熸枻鎷烽敓鏂ゆ嫹Tpwm = 2*TBPRD*Ttbclk
		閿熸枻鎷烽敓鏂ゆ嫹Tpwm=50us閿熸枻鎷稵tbclk=SYSCLKOUT/(HSPCLKDIV*CLKDIV)閿熸枻鎷稨SPCLKDIV = 1閿熸枻鎷烽敓鏂ゆ嫹EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0U閿熸枻鎷烽敓鏂ゆ嫹閿熸枻鎷�
		CLKDIV = 1閿熸枻鎷烽敓鏂ゆ嫹EPwm1Regs.TBCTL.bit.CLKDIV = 0U閿熸枻鎷烽敓鏂ゆ嫹
		閿熸枻鎷稵tbclk = 1/SYSCLKOUT = 1/120MHZ

		Tpwm = 2*TBPRD*Ttbclk閿熸枻鎷风煡 TBPRD =Tpwm/(2*Ttbclk) = 50us*120MHZ / 2 = 3000
	*/
    Uint16 uiPWMCountSet = (Uint16)VAL_EPWM_PRD;//set to 3000,50us,20khz;		set to 5340,8.9khz,110.236us
    EALLOW;

    SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; /*閿熸枻鎷锋鏃堕敓鏂ゆ嫹鍚岄敓鏂ゆ嫹鏃堕敓鏂ゆ嫹*/

    EPwm1Regs.ETSEL.bit.INTEN = 0; /*閿熸枻鎷锋ePWM1閿熷彨璁规嫹*/
    EPwm1Regs.ETSEL.bit.INTSEL = 1U; /*閿熸枻鎷烽敓鏂ゆ嫹閿熸枻鎷烽敓鏂ゆ嫹涓�0鏃堕敓鏂ゆ嫹閿熸枻鎷烽敓鍙鎷�*/
    EPwm1Regs.ETPS.bit.INTPRD = 1U;  /*閿熸枻鎷蜂竴閿熸枻鎷烽敓閾扮》鎷烽敓鏂ゆ嫹閿熸枻鎷烽敓鏂ゆ嫹閿熷彨璁规嫹*/
    EPwm1Regs.TBPRD = uiPWMCountSet;  /*閿熸枻鎷烽敓鏂ゆ嫹涓�50us閿熸枻鎷烽敓鏂ゆ嫹*/
    EPwm1Regs.TBCTR = 0X0000U;
    EPwm1Regs.TBCTL.bit.CTRMODE = 2U;    /*ePWM1閿熸枻鎷烽敓鏂ゆ嫹妯″紡閫夐敓鏂ゆ嫹浣�   */  //zr閿熸枻鎷烽敓鏂ゆ嫹-閿熼摪纭锋嫹閿熸枻鎷�
    EPwm1Regs.TBCTL.bit.PHSEN = 0U;      /*ePWM1閿熸枻鎷蜂綅閿熶茎杈炬嫹閿熸枻鎷蜂娇閿熸枻鎷蜂綅 */  //zr 閿熸枻鎷烽敓鏂ゆ嫹鎷囬敓鏂ゆ嫹閿熸枻鎷烽敓琛楁：甯嫹閿燂拷1閿燂拷7
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0U;  /*ePWM1鏃堕敓鏂ゆ嫹1閿熸枻鎷烽敓鏂ゆ嫹棰戜綅    */ //zr閿熸枻鎷烽敓鏂ゆ嫹鏃堕敓鏂ゆ嫹鏃堕敓鎺ュ嚖鎷烽鍊� 閿熸枻鎷�1閿熸枻鎷烽閿熸枻鎷�
    EPwm1Regs.TBCTL.bit.CLKDIV = 0U;     /*ePWM1鏃堕敓鏂ゆ嫹2閿熸枻鎷烽敓鏂ゆ嫹棰戜綅    */ //zr鏃堕敓鏂ゆ嫹鏃堕敓鎺ュ嚖鎷烽鍊�1
    EPwm1Regs.TBCTL.bit.SYNCOSEL = 3U;   /*ePWM1鍚岄敓鏂ゆ嫹閿熸枻鎷烽敓缁炵櫢鎷烽敓杞匡拷1閿燂拷7   */ //zr閿熸枻鎷锋鍚岄敓鏂ゆ嫹閿熻剼鐚存嫹閿熸枻鎷烽敓锟�1閿燂拷7
    EPwm1Regs.TBCTL.bit.PRDLD = 0U;      /*ePWM1褰遍敓鏂ゆ嫹妯″紡閫夐敓鏂ゆ嫹浣�   */ //zr閿熸枻鎷烽敓鏂ゆ嫹閿熸枻鎷烽敓鏂ゆ嫹閿熸枻鎷峰�间负0鏃堕敓鏂ゆ嫹閿熻妭瀵勮揪鎷烽敓鏂ゆ嫹TBPRD瑁呴敓鏂ゆ嫹褰遍敓鎺ュ瘎杈炬嫹閿熸枻鎷烽敓鏂ゆ嫹鍊�
    EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0U;/*CMPA set to shadow mode*/ //zr閿熸枻鎷烽敓鏂ゆ嫹鍐夐敓绱搁敓渚ヨ揪鎷烽敓鏂ゆ嫹閿熸枻鎷烽敓鏂ゆ嫹妯″紡閿熸枻鎷峰奖閿熸枻鎷疯閿熸枻鎷锋ā寮忛敓鏂ゆ嫹CPU閿熸枻鎷峰奖閿熸帴瀵勮揪鎷烽敓鏂ゆ嫹鍐欓敓鏂ゆ嫹鍊�
    EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0U;/*CMPB set to shadow mode*/
    EPwm1Regs.CMPCTL.bit.LOADAMODE = 0U;/*Load compare value when TBCTR == 0 */ //褰遍敓鏂ゆ嫹瑁呴敓鏂ゆ嫹妯″紡閿熼摪锝忔嫹瑁呴敓鏂ゆ嫹閿熸枻鎷烽敓鏂ゆ嫹閫夐敓鏂ゆ嫹妯″紡閿熸枻鎷稢TR = ZERO
    EPwm1Regs.CMPCTL.bit.LOADBMODE = 0U;/*Load compare value when TBCTR == 0*/
    /*Action-Qualifier Output A/B Control Register*/
    EPwm1Regs.AQCTLA.bit.CAU = 2U;/*Set: force EPWM1A output high*/ //閿熸枻鎷烽敓杈冪》鎷烽敓鏂ゆ嫹鏃堕敓鏂ゆ嫹閿熺煫闈╂嫹
    EPwm1Regs.AQCTLA.bit.CAD = 1U;/*Clear: force EPWM1A output low*/ //閿熸枻鎷烽敓閾扮》鎷烽敓鏂ゆ嫹鏃堕敓鏂ゆ嫹閿熺煫纰夋嫹
    EPwm1Regs.AQCTLB.bit.CAU = 2U;/*Set: force EPWM1B output high*/
    EPwm1Regs.AQCTLB.bit.CAD = 1U;/*Clear: force EPWM1B output low*/

    /*Action-Qualifier Continuous Software Force Register,set EPWM1A&B initial state*/

    /*Initialize ePWM2*/
    /*Time-Base Period Register*/
    EPwm2Regs.TBPRD = uiPWMCountSet;
    /*Time-Base Counter Register*/
    EPwm2Regs.TBCTR = 0X0000U;/* Clear counter*/
    /*Time-Base Control Register*/
    EPwm2Regs.TBCTL.bit.CTRMODE = 2U;/*up-down-count mode*/
    EPwm2Regs.TBCTL.bit.PHSEN = 0U;/*Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS)*/
    /*TBCLK = SYSCLKOUT / (HSPCLKDIV 閿熸枻鎷� CLKDIV)*/
    EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0U;
    EPwm2Regs.TBCTL.bit.CLKDIV = 0U;
    EPwm2Regs.TBCTL.bit.SYNCOSEL = 3U;/*Disable EPWM2SYNCO signal*/
    EPwm2Regs.TBCTL.bit.PRDLD = 0U;
    /*Counter-Compare Control Register*/
    EPwm2Regs.CMPCTL.bit.SHDWAMODE = 0U;/*CMPA set to shadow mode*/
    EPwm2Regs.CMPCTL.bit.SHDWBMODE = 0U;/*CMPB set to shadow mode*/
    EPwm2Regs.CMPCTL.bit.LOADAMODE = 0U;/*Load compare value when TBCTR == 0 */
    EPwm2Regs.CMPCTL.bit.LOADBMODE = 0U;/*Load compare value when TBCTR == 0  */
    /*Action-Qualifier Output A/B Control Register*/
    EPwm2Regs.AQCTLA.bit.CAU = 2U;/*Set: force EPWM2A output hight*/
    EPwm2Regs.AQCTLA.bit.CAD = 1U;/*Clear: force EPWM2A output low*/
    EPwm2Regs.AQCTLB.bit.CAU = 2U;/*Set: force EPWM2B output high */
    EPwm2Regs.AQCTLB.bit.CAD = 1U;/*Clear: force EPWM2B output low  */

    /*Action-Qualifier Continuous Software Force Register,set EPWM1A&B initial state*/

    /*Initialize ePWM3*/
    /*Time-Base Period Register*/
    EPwm3Regs.TBPRD = uiPWMCountSet;
    /*Time-Base Counter Register*/
    EPwm3Regs.TBCTR = 0X0000U;/* Clear counter*/
    /*Time-Base Control Register*/
    EPwm3Regs.TBCTL.bit.CTRMODE = 2U;/*up-down-count mode*/
    EPwm3Regs.TBCTL.bit.PHSEN = 0U;/*Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS)*/
    /*TBCLK = SYSCLKOUT / (HSPCLKDIV 閿熸枻鎷� CLKDIV)*/
    EPwm3Regs.TBCTL.bit.HSPCLKDIV = 0U;
    EPwm3Regs.TBCTL.bit.CLKDIV = 0U;
    EPwm3Regs.TBCTL.bit.SYNCOSEL = 3U;/*Disable EPWM3SYNCO signal*/
    EPwm3Regs.TBCTL.bit.PRDLD = 0U;
    /*Counter-Compare Control Register*/
    EPwm3Regs.CMPCTL.bit.SHDWAMODE = 0U;/*CMPA set to shadow mode*/
    EPwm3Regs.CMPCTL.bit.SHDWBMODE = 0U;/*CMPB set to shadow mode*/
    EPwm3Regs.CMPCTL.bit.LOADAMODE = 0U;/*Load compare value when TBCTR == 0 */
    EPwm3Regs.CMPCTL.bit.LOADBMODE = 0U;/*Load compare value when TBCTR == 0*/
    /*Action-Qualifier Output A/B Control Register*/
    EPwm3Regs.AQCTLA.bit.CAU = 2U;/*Set: force EPWM1A output high*/
    EPwm3Regs.AQCTLA.bit.CAD = 1U;/*Clear: force EPWMxA output low*/
    EPwm3Regs.AQCTLB.bit.CAU = 2U;/*Set: force EPWM1B output high*/
    EPwm3Regs.AQCTLB.bit.CAD = 1U;/*Clear: force EPWMxB output low*/

    /*Action-Qualifier Continuous Software Force Register,set EPWM3A&B initial state*/

    SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;  /*浣块敓鏂ゆ嫹鏃堕敓鏂ゆ嫹鍚岄敓鏂ゆ嫹鏃堕敓鏂ゆ嫹*/

    EDIS;

    return;
}

void EpwmDBConfig(void)
{
    EALLOW;

    EPwm1Regs.DBCTL.bit.IN_MODE = 0U;
    EPwm1Regs.DBCTL.bit.POLSEL = 2U;
    EPwm1Regs.DBCTL.bit.OUT_MODE = 3U;
    EPwm1Regs.DBRED = 120U;// 120 * TBCLK = 120 / 6000 * 50us = 1us
    EPwm1Regs.DBFED = 120U;

    EPwm2Regs.DBCTL.bit.IN_MODE = 0U;
    EPwm2Regs.DBCTL.bit.POLSEL = 2U;
    EPwm2Regs.DBCTL.bit.OUT_MODE = 3U;
    EPwm2Regs.DBRED = 120U;// 120 * TBCLK = 120 / 6000 * 50us = 1us
    EPwm2Regs.DBFED = 120U;

    EPwm3Regs.DBCTL.bit.IN_MODE = 0U;
    EPwm3Regs.DBCTL.bit.POLSEL = 2U;
    EPwm3Regs.DBCTL.bit.OUT_MODE = 3U;
    EPwm3Regs.DBRED = 240U;// 240 * TBCLK = 240 / 6000 * 50us = 2us
    EPwm3Regs.DBFED = 240U;// 240 * TBCLK = 240 / 6000 * 50us = 2us

    EDIS;
}



void InitEPwmGpio(void)
{
    EALLOW;
    //mux
    GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0;    // Enable pull-up on GPIO0 (EPWM1A)
    GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0;    // Enable pull-up on GPIO1 (EPWM1B)
    GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0;    // Enable pull-up on GPIO2 (EPWM1A)
    GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0;    // Enable pull-up on GPIO3 (EPWM1B)
    GpioCtrlRegs.GPAPUD.bit.GPIO4 = 0;    // Enable pull-up on GPIO4 (EPWM1A)
    GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0;    // Enable pull-up on GPIO5 (EPWM1B)

    GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1U;   // Configure GPIO0 as EPWM1A
    GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1U;   // Configure GPIO1 as EPWM1B
    GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1U;   // Configure GPIO2 as EPWM2A
    GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1U;   // Configure GPIO3 as EPWM2B
    GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1U;   // Configure GPIO4 as EPWM3A
    GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1U;   // Configure GPIO5 as EPWM3B
    EDIS;
}

#define LOS_ADDR1  0x88
#define LOS_ADDR2  0x89
#define LOS_ADDR3  0x8A
#define LOS_ADDR4  0x8B
#define LOS_ADDR5  0x8C
#define LOS_ADDR6  0x8D
#define LOS_ADDR7  0x8E
#define LOS_ADDR8  0x91
#define LOS_ADDR9  0x92
void InitRdc(void)
{
    //Uint16 rdcErrValue = 0U;

//	DO_RDC_SAMPLE = 1U; //(旋变解调芯片采样信号)
	DO_RDC_RST = 1U;
	DELAY_US(1000UL);
	DO_RDC_RST = 0U;//(旋变复位输出信号)置为0，延时1ms后置为1；
	DELAY_US(1000UL);
	DO_RDC_RST = 1U;
	DELAY_US(25000UL);


//	DIS_RDC_RES1 = 	1U;//(旋变分辨率选择1)置为1(12位)；
//	DIS_RDC_RES0 = 0U;//(旋变分辨率选择0)置为0(12位)；



//////////////////////清故障寄存器//////////////////////////////////
//	DO_RDC_SAMPLE = 1U; //(旋变解调芯片采样信号)
//	DELAY_US(1000UL);
//	DO_RDC_SAMPLE = 0U;
//	DELAY_US(5UL);
//	DO_RDC_SAMPLE = 1U;
//	DELAY_US(5UL);
//	DO_RDC_A0 = 1U;//旋变模式选择信号0置为1，旋变模式选择信号1置为1，配置成配置模式
//	DO_RDC_A1 = 1U;
//	DELAY_US(5UL);
//	*(Uint32 *)ADD_RDC_POS = 0xFFU;		//向该地址中写入0xFF

	//RdcConfig(LOS_ADDR1);//LOS阈值寄存器配置
	//RdcConfig(LOS_ADDR2);//DOS超量程寄存器
	//RdcConfig(LOS_ADDR3);//DOS失配寄存器
	//RdcConfig(LOS_ADDR4);//DOS复位最大阈值寄存器
	//RdcConfig(LOS_ADDR5);//DOS复位最小阈值寄存器
	//RdcConfig(LOS_ADDR6);//LOT上限
	//RdcConfig(LOS_ADDR7);//LOT下限
	//RdcConfig(LOS_ADDR8);//激励频率
	//RdcConfig(LOS_ADDR9);//控制

	DO_RDC_SOE = 1U;//(旋变串行输出使能信号)置为1(并行输出)；

	DELAY_US(5UL);

	DO_RDC_A0 = 1U;//A0
	DELAY_US(5UL);
	DO_RDC_A1 = 1U;//A1
	DELAY_US(500UL);

	*(Uint16 *)ADD_RDC_POS = 0x91;
	DELAY_US(1UL);
	*(Uint16 *)ADD_RDC_POS = 0x28;//0x28=10k; 0x14=5k

	DELAY_US(5UL);
	DO_RDC_A0 = 0U;//A0
	DELAY_US(5UL);
	DO_RDC_A1 = 0U;//A1

//	DELAY_US(5UL);
//	//rdcErrValue = *(Uint32 *)ADD_RDC_POS;
//	DELAY_US(5UL);
//	DO_RDC_A0 = 0U;//A0,A1，
//	DO_RDC_A1 = 0U;
//	DELAY_US(5UL);
	DO_RDC_SAMPLE = 0U;
	DELAY_US(5UL);
	DO_RDC_SAMPLE = 1U;
////////////////////////////////////////////////////////////////////



}

void InitECanaGpio(void)
{
    EALLOW;

    //
    // Enable internal pull-up for the selected CAN pins
    // Pull-ups can be enabled or disabled by the user.
    // This will enable the pullups for the specified pins.
    // Comment out other unwanted lines.
    //
    //GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0;	  // Enable pull-up for GPIO30 (CANRXA)
    GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up for GPIO18 (CANRXA)

    //GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0;	 //Enable pull-up for GPIO31 (CANTXA)
    GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0;  //Enable pull-up for GPIO19 (CANTXA)

    //
    // Set qualification for selected CAN pins to asynch only
    // Inputs are synchronized to SYSCLKOUT by default.
    // This will select asynch (no qualification) for the selected pins.
    //
    //GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3;   // Asynch qual for GPIO30 (CANRXA)
    GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3;  // Asynch qual for GPIO18 (CANRXA)

    //
    // Configure eCAN-A pins using GPIO regs
    // This specifies which of the possible GPIO pins will be eCAN functional
    // pins.
    //
    //GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1;	// Configure GPIO30 for CANRXA
    GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3;	// Configure GPIO18 for CANRXA
    //GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1;	// Configure GPIO31 for CANTXA
    GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 3;	// Configure GPIO19 for CANTXA

    EDIS;
}

void InitECan(void)
{
    //
    // Create a shadow register structure for the CAN control registers. This
    // is needed, since only 32-bit access is allowed to these registers.
    // 16-bit access to these registers could potentially corrupt the register
    // contents or return false data. This is especially true while writing
    // to/reading from a bit (or group of bits) among bits 16 - 31
    //
    struct ECAN_REGS ECanaShadow;

    EALLOW;		// EALLOW enables access to protected bits

    //
    // Configure eCAN RX and TX pins for CAN operation using eCAN regs
    //
    ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
    ECanaShadow.CANTIOC.bit.TXFUNC = 1;
    ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;

    ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
    ECanaShadow.CANRIOC.bit.RXFUNC = 1;
    ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;

    //
    // Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31)
    // HECC mode also enables time-stamping feature
    //
    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.SCB = 1;
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

    //
    // Initialize all bits of 'Master Control Field' to zero
    // Some bits of MSGCTRL register come up in an unknown state. For proper
    // operation, all bits (including reserved bits) of MSGCTRL must be
    // initialized to zero
    //
    ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;

    //
    // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
    // as a matter of precaution.
    //
    ECanaRegs.CANTA.all	= 0xFFFFFFFF;       // Clear all TAn bits

    ECanaRegs.CANRMP.all = 0xFFFFFFFF;      // Clear all RMPn bits

    ECanaRegs.CANGIF0.all = 0xFFFFFFFF;     // Clear all interrupt flag bits
    ECanaRegs.CANGIF1.all = 0xFFFFFFFF;

    //
    // Configure bit timing parameters for eCANA
    //
    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.CCR = 1 ;            // Set CCR = 1
    ECanaShadow.CANMC.bit.ABO = 1 ;            // Set ABO = 1
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

    ECanaShadow.CANES.all = ECanaRegs.CANES.all;

    do
    {
        ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    } while(ECanaShadow.CANES.bit.CCE != 1 );  	// Wait for CCE bit to be set

    ECanaShadow.CANBTC.all = 0;
    //SYSCLKOUT = 120 MHz
    //CAN clock = 60 MHz
    //Bit time = TSEG2REG + 1 + TSEG2REG + 1 + 1 = 15
    //Bit rate = CAN clock / ((BRPREG + 1) * Bit time) = 60 MHz / (32 * 15) = 125 Kbps
    //TQ = (31+1) / 60MHz = 0.533us
    //SP = 66%
    ECanaShadow.CANBTC.bit.BRPREG = 31;
    ECanaShadow.CANBTC.bit.TSEG2REG = 4;
    ECanaShadow.CANBTC.bit.TSEG1REG = 8;
    //samples three times
    ECanaShadow.CANBTC.bit.SAM = 1;
    ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;

    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.CCR = 0 ;            // Set CCR = 0
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

    ECanaShadow.CANES.all = ECanaRegs.CANES.all;

    do
    {
        ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    } while(ECanaShadow.CANES.bit.CCE != 0 );// Wait for CCE bit to be  cleared

    //--------------------------------------------------TX config-------------------------------------------
    ECanaRegs.CANME.all = 0;		// Required before writing the MSGIDs

    //dir
	ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
	ECanaShadow.CANMD.bit.MD0 = 0;
	ECanaShadow.CANMD.bit.MD1 = 0;
	ECanaShadow.CANMD.bit.MD2 = 0;
	ECanaShadow.CANMD.bit.MD3 = 1;
	ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;
	//id
	ECanaMboxes.MBOX0.MSGID.all = 0x01900000; // bit31:IDE=0    bit30:AME=0    bit29:AAM=0    bit28-18:ID=0 00011 00100    bit17-0:rsv
	ECanaMboxes.MBOX1.MSGID.all = 0x01900000; // bit31:IDE=0    bit30:AME=0    bit29:AAM=0    bit28-18:ID=0 00011 00100    bit17-0:rsv
	ECanaMboxes.MBOX2.MSGID.all = 0x01900000; // bit31:IDE=0    bit30:AME=0    bit29:AAM=0    bit28-18:ID=0 00011 00100    bit17-0:rsv
	ECanaMboxes.MBOX3.MSGID.all = 0x020C0000; // bit31:IDE=0    bit30:AME=0    bit29:AAM=0    bit28-18:ID=0 00100 00011    bit17-0:rsv
	//enable
	ECanaShadow.CANME.all = ECanaRegs.CANME.all;
	ECanaShadow.CANME.bit.ME0 = 1;
	ECanaShadow.CANME.bit.ME1 = 1;
	ECanaShadow.CANME.bit.ME2 = 1;
	ECanaShadow.CANME.bit.ME3 = 1;
	ECanaRegs.CANME.all = ECanaShadow.CANME.all;
	//dlc
	ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8;
	ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 4;
	ECanaMboxes.MBOX2.MSGCTRL.bit.DLC = 6;

	//data
	ECanaMboxes.MBOX0.MDL.all = 0;
	ECanaMboxes.MBOX0.MDH.all = 0;
	ECanaMboxes.MBOX1.MDL.all = 0;
	ECanaMboxes.MBOX1.MDH.all = 0;
	ECanaMboxes.MBOX2.MDL.all = 0;
	ECanaMboxes.MBOX2.MDH.all = 0;

    EDIS;
}



void InitRdcGpio(void)
{
    EALLOW;
    //mux
    GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 0U;	//RDC_RES0
    GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 0U;	//RDC_RES1
    GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 0U;	//RDC_SOE
    GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 0U;	//RDC_SAMPLE
    GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 0U;	//RDC_RST
//    GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 0U;	//RDC_A0
//    GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 0U;	//RDC_A1
//    GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 0U;	//RDC_DOS
//    GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 0U;	//RDC_LOT
    //dir
	GpioCtrlRegs.GPBDIR.bit.GPIO48 = 1U;	//RDC_RES0
	GpioCtrlRegs.GPBDIR.bit.GPIO49 = 1U;	//RDC_RES1
	GpioCtrlRegs.GPBDIR.bit.GPIO50 = 1U;	//RDC_SOE
	GpioCtrlRegs.GPBDIR.bit.GPIO51 = 1U;	//RDC_SAMPLE
	GpioCtrlRegs.GPBDIR.bit.GPIO52 = 1U;	//RDC_RST
//	GpioCtrlRegs.GPBDIR.bit.GPIO53 = 1U;	//RDC_A0
//	GpioCtrlRegs.GPBDIR.bit.GPIO54 = 1U;	//RDC_A1
//	GpioCtrlRegs.GPBDIR.bit.GPIO55 = 0U;	//RDC_DOS
//	GpioCtrlRegs.GPBDIR.bit.GPIO56 = 0U;	//RDC_LOT

    EDIS;
}

void InitSysGpio(void)
{
    EALLOW;

    GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 0U;	//INPUT:HALL
    GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 0U;	//INPUT:HALL
    GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 0U;	//INPUT:HALL
    GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 0U;   //OUTPUT:MOTOR_EN
    GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 0U;   //OUTPUT:LED
    GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 0U;	//OUTPUT:TEST
    GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 0U;	//OUTPUT:TEST
    GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 0U;   //OUTPUT:TEST
    GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 0U;   //OUTPUT:TEST

    GpioCtrlRegs.GPADIR.bit.GPIO7 = 0U;
	GpioCtrlRegs.GPADIR.bit.GPIO9 = 0U;
	GpioCtrlRegs.GPADIR.bit.GPIO11 = 0U;
	GpioCtrlRegs.GPADIR.bit.GPIO13 = 1U;
	GpioCtrlRegs.GPADIR.bit.GPIO31 = 1U;
    GpioCtrlRegs.GPBDIR.bit.GPIO58 = 1U;
	GpioCtrlRegs.GPBDIR.bit.GPIO59 = 1U;
	GpioCtrlRegs.GPBDIR.bit.GPIO60 = 1U;
	GpioCtrlRegs.GPBDIR.bit.GPIO61 = 1U;

    EDIS;
}

void InitSoftware(void)
{
    memset(&g_SysData, 0, sizeof(g_SysData));
    memset(&g_CanMsg, 0, sizeof(g_CanMsg));
    memset(&g_PlusGen, 0, sizeof(g_PlusGen));
    g_CanMsg.CommPeriod = 500U;
    return;
}



void InitECAP(void)
{
    EALLOW;

    SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 1U;
    //SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 1U;
    //SysCtrlRegs.PCLKCR1.bit.ECAP4ENCLK = 1U;

    PieCtrlRegs.PIEIER4.bit.INTx2 = 1U;//ECAP2
    //PieCtrlRegs.PIEIER4.bit.INTx3 = 1U;//ECAP3
    //PieCtrlRegs.PIEIER4.bit.INTx4 = 1U;//ECAP4

    GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 3U;   //HALL-A

    EDIS;

    IER = IER | BIT3;


	ECap2Regs.ECEINT.all = 0x0;
	ECap2Regs.ECCLR.all = 0x0;
	ECap2Regs.ECCTL1.bit.CAPLDEN = 0;
	ECap2Regs.ECCTL2.bit.TSCTRSTOP = 0;

	ECap2Regs.ECCTL1.bit.CAP1POL = 1;//一级事件捕获下降沿
//	ECap2Regs.ECCTL1.bit.CAP2POL = 1;//二级事件捕获下降沿
//	ECap2Regs.ECCTL1.bit.CAP3POL = 0;//三级事件捕获上升沿
//	ECap2Regs.ECCTL1.bit.CAP4POL = 1;//四级事件捕获下降沿

	ECap2Regs.ECCTL1.bit.CTRRST1 = 1;//一级事件捕获后重置计数器
//	ECap2Regs.ECCTL1.bit.CTRRST2 = 1;//二级事件捕获后重置计数器
//	ECap2Regs.ECCTL1.bit.CTRRST3 = 1;//三级事件捕获后重置计数器
//	ECap2Regs.ECCTL1.bit.CTRRST4 = 1;//四级事件捕获后重置计数器

	ECap2Regs.ECCTL1.bit.CAPLDEN = 0;//禁止事件捕捉时CAP寄存器装载计数器的值
	ECap2Regs.ECCTL1.bit.PRESCALE = 0;//对外部信号不分频
	ECap2Regs.ECCTL2.bit.CAP_APWM = 0;//捕获模式ECAP
	ECap2Regs.ECCTL2.bit.CONT_ONESHT = 0;//连续模式
	ECap2Regs.ECCTL2.bit.SYNCO_SEL = 3;//屏蔽同步信号输出
	ECap2Regs.ECCTL2.bit.SYNCI_EN = 0;//屏蔽同步输入操作

	ECap2Regs.ECEINT.all = 0x0;//关闭所有CAP中断
	ECap2Regs.ECCLR.all = 0xFFFF;//清除所有中断标志位
	ECap2Regs.ECCTL2.bit.TSCTRSTOP = 0;//启动CAP计数器
	ECap2Regs.ECEINT.bit.CEVT1 = 1;//使能1级事件中断，即当发生第1次捕获时进入中断。
//	ECap2Regs.ECEINT.bit.CEVT2 = 1;//使能2级事件中断，即当发生第2次捕获时进入中断。
//	ECap2Regs.ECEINT.bit.CEVT3 = 1;//使能3级事件中断，即当发生第3次捕获时进入中断。
//	ECap2Regs.ECEINT.bit.CEVT4 = 1;//使能4级事件中断，即当发生第4次捕获时进入中断。
}

void InitADC(void)
{
//    EALLOW;
//
//    ADC_cal();
//
//    EDIS;

    AdcRegs.ADCTRL1.bit.RESET = 1U;         /*ADC module software reset*/
    AdcRegs.ADCTRL3.bit.ADCBGRFDN = 0X3U;   /*The bandgap and reference circuitry is powered up*/
    AdcRegs.ADCTRL3.bit.ADCPWDN = 0X1U;     /*The analog circuitry inside the core is powered up*/
    AdcRegs.ADCTRL1.bit.CPS = 1U;           /*锟节猴拷时锟斤拷预锟斤拷锟斤拷锟斤拷锟斤拷值锟斤拷1*/
    AdcRegs.ADCTRL3.bit.ADCCLKPS = 15U;     /*锟斤拷时锟接凤拷频*/
    AdcRegs.ADCTRL1.bit.ACQ_PS = 15U;       /*锟斤拷锟斤拷锟绞憋拷锟轿伙拷锟轿�1锟�7*/
    AdcRegs.ADCTRL3.bit.SMODE_SEL = 0U;     /*Sequential sampling mode is selected*/
    AdcRegs.ADCTRL1.bit.SEQ_CASC = 1U;      /*Cascaded mode. SEQ1 and SEQ2 operate as a single 16-state sequencer (SEQ) */
    AdcRegs.ADCTRL1.bit.CONT_RUN = 1U;      /*Continuous run*/
    AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 1U;      /**/

    /*使锟斤拷8锟斤拷转锟斤拷通锟斤拷*/
    AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 4U;
    AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0U;    //ADCINA0	GND
    AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 1U;    //ADCINA1	MOTOR_V
    AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 2U;	 //ADCINA2	MOTOR_I
    AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 8U;    //ADCINB0	GND
    AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 7U;    //ADCINA7	Temperate
//    AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 10U;   //ADCINB2	RVDT3
//    AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 11U;   //ADCINB3	RVDT4
//    AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 12U; 	 //ADCINB5	GND

    return;
}
/*---------------------------------------------------------------------------
 * End of file.
 *--------------------------------------------------------------------------*/



